/*
Name: BusInteface.sv
Description: Defines the interface between the CPU and Bus Activity Monitor
Author: ChinniKrishna Kothapalli
*/
interface BusInterface;
//Generic 8086 Bus
logic Clock;			//System Wide Clock
logic [15:0] AddrData;		//Address and Data Multiplexed
logic [19:16]AddrStatus;	//Address and Status Multiplexed
logic RD;			//Active Low Read Signal
logic WR;			//Active Low Write Signal
logic IOM;			//Active Low-I/O, Active High-Memory
logic ALE;			//Address Latch Enable
logic Ready;			//Ready to indicate data is ready in Read
logic Reset;			//Global Reset.
logic NMI;			//Non Maskable Interrupt
logic Intr;			//Interrupt
logic BHE;			//Bus High Enable
logic MnMx;			//Minimum Maximum Mode Selection
logic Hold;
logic HLDA;
logic DTR;
logic DEN;
logic INTA;
logic Test;

//Modport which connects CPU to BusAcitivity Monitor
modport CPUPort(
				 output Clock,
				 output AddrData,
				 output AddrStatus,
				 output Ready,
				 output IOM,
				 output RD,
				 output WR,
				 output ALE,
				 output Reset);

//Modport which connects CPU to BusAcitivity Monitor
modport BamInputPort(
				 input Clock,
				 input AddrData,
				 input AddrStatus,
				 input Ready,
				 input IOM,
				 input RD,
				 input WR,
				 input ALE,
				 input Reset);

endinterface


